Integrated circuit field effect transistors are widely used in microelectronic devices including, but not limited to, microprocessors, logic devices and memory devices. As is well known to those having skill in the art, an integrated circuit insulated gate field effect transistor, often referred to as a MOSFET or MOS transistor, includes an insulated gate on the face of an integrated circuit substrate, between spaced apart source/drain regions in the integrated circuit substrate.
As the integration density of integrated circuits continues to increase, high performance gate electrodes for field effect transistors are desirable. In particular, it is generally desirable that the gate electrode material have low resistance and chemical stability, so as not to react with the gate insulating film during subsequent thermal treatments. The gate electrode material should also preferably have good adhesive strength so that it is not deformed by stress. Finally, it is preferred that the gate electrode material be readily etched in fine patterns to permit high device integration.
In order to meet at least some of these criteria, it has been proposed to form a multilayer gate electrode. In order to provide thermal stability and a good work function, it has been proposed to form a multilayer gate electrode including a first conductive layer of a metal nitride film such as titanium nitride (TiN) and a second conductive layer comprising a low resistance metal layer, on the first conductive layer. The low resistance metal layer may be, for example, a metal film comprising tungsten (W), titanium (Ti), titanium disilicide (TiSi.sub.2) or copper (Cu).
The titanium nitride can provide an excellent diffusion barrier to reduce and preferably prevent diffusion from the low resistance metal layer into the gate oxide. Moreover, the work function of titanium nitride is almost the same as that of intrinsic silicon. Therefore, when the titanium nitride film is formed on the gate oxide film, complementary MOS transistors (referred to as "CMOS" transistors) can have a surface channel, to thereby improve the characteristics of the CMOS circuit.
FIG. 1 is a cross-sectional view of a conventional MOS transistor which uses a multilayer gate electrode. As shown in FIG. 1, a conventional MOS transistor includes a gate oxide film 102 on a face of an integrated circuit substrate such as a semiconductor substrate 100. A titanium nitride film 106 and a low resistance metal layer 108 such as a tungsten film, are formed on the gate oxide film 102 to provide a multilayer gate electrode.
Unfortunately, a conventional MOS transistor as described in FIG. 1 may encounter problems due to etching during fabrication thereof. In particular, in order to use the titanium nitride film 106 in the multilayer gate electrode, the etching selectivity between the titanium nitride film 106 and the gate insulating film 102 such as a silicon dioxide film, should be high. Unfortunately, it may be difficult to dry etch the device under these conditions. Accordingly, when dry etched, etching damage may occur in the gate oxide film under the edges of the gate electrode and in the semiconductor substrate under the gate oxide film. When this etching damage occurs, leakage current may flow between the gate electrode and the semiconductor substrate, thereby degrading the device characteristics.
It is known to use a thermal oxidation process to cure the gate oxide damage which may occur during the dry etch. Unfortunately, thermal oxidation may produce stress due to expansion, adjacent the titanium nitride film, and thereby may degrade the adhesion of the titanium nitride film.
A publication entitled "Novel Polysilicon/TiN Stacked-Gate Structure for Fully-Depleted SOI/CMOS" by Hwang et al., IEDM Technical Digest, International Electrode Devices Meeting, San Francisco, Calif., Dec. 13-16, 1992, pp. 345-348, describes an example of fabricating a gate electrode for a field effect transistor using wet etching. According to this publication, a very thin TiN layer (about 40 nm) was deposited by reactive sputtering on a 15-nm thermally-grown gate oxide, and was followed by deposition of a 300-nm thick polysilicon layer. A blanket phosphorus implant was used to dope the polysilicon. During the polysilicon gate etch, the underlying thin TiN layer serves as an excellent etch stop. The TiN was wet-etched after formation of a 100-nm low-temperature oxide spacer. A second oxide spacer was then used to completely seal the exposed TiN edges.
Unfortunately, when a transistor is fabricated using wet etching as described above, it may be difficult to control the wet etching characteristics, such as etching uniformity and etching rates. Also, it may be difficult to form gate electrodes of uniform size due to isotropic etching. Moreover, the width of the bottom gate in the gate electrode which comprises titanium nitride, may be increased. The insulation margin with respect to the gate electrode may thereby be reduced, which may make it difficult to highly integrate the field effect transistor devices.